The present disclosure generally relates to integrated circuits, and more particularly to the threshold voltage of field effect transistors.
The need to remain cost and performance competitive in the production of semiconductor devices has caused device density to continually increase in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in the design and fabrication of field effect transistors (FETs), such as those used in CMOS technologies. FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.). One of the fundamental parameters of FET design is the threshold voltage (VT).
Most integrated circuits require transistors with different threshold voltages to achieve tradeoff between power and performance. The threshold voltage of a FET is determined primarily by the channel doping, the gate dielectric thickness, and gate length. Present methods for providing FETs with different threshold voltages on the same chip require a different masking step followed by a specialized channel ion implant for each different threshold voltage desired. Thus, a chip that requires FETs with five different threshold voltages requires five different masking steps, each followed by a specialized implant of varying dose and energy designed to adjust the threshold voltage. This greatly increases the process complexity with the attending problems, all of which serve to drive chip yield down and costs up.